The invention relates to using communication cycles.
Computer systems typically have expansion card slots for receiving and electrically coupling expansion cards to an expansion bus of the computer system. The expansion bus may be one of several types, such as an Industry Standard Architecture (ISA) bus, an Extended Industry Standard Architecture (EISA) bus or a Peripheral Component Interconnect (PCI) bus.
The expansion bus typically is connected to many bus devices (e.g., bus devices introduced through the expansion card), each of which use a bus transaction, or bus cycle (e.g., a normal read cycle or burst read cycle), on the bus to transfer data between devices. A PCI bus device that initiates the bus cycle is known as an initiator, or master, and a PCI bus device that is targeted by the bus cycle is known as a target, or slave. Depending on the type of bus cycle, the initiator may receive (for a read operation) or furnish (for a write operation) data that is received (for a write operation) or furnished (for a read operation) by the target.
Only one initiator at a time may "own" the bus. To determine bus ownership, the computer system typically has a bus arbiter which receives requests from all bus devices (i.e., all potential initiators) that desire to initiate a cycle on the bus, and based on a predetermined priority scheme, the arbiter selectively grants access to the requesting bus devices. The arbiter indicates the grant to a particular bus device by activating a bus grant signal that is specifically assigned to the bus device. Once granted access to the bus, the bus device waits for any preexisting bus cycle to complete before initiating its own bus cycle.